stk_arch_arm-cortex-m.h File Reference

Platform port for ARM Cortex-M. More...

#include "stk_common.h"

Include dependency graph for stk_arch_arm-cortex-m.h:

Go to the source code of this file.

Classes
class	stk::PlatformArmCortexM
	Concrete implementation of IPlatform driver for the Arm Cortex-M0, M3, M4, M7 processors. More...
struct	stk::hw::ExceptionFrame
	ARMv7-M/ARMv8-M hardware exception frame (8 words, highest address on the stack). More...
struct	stk::FaultContext
	ARMv7-M/ARMv8-M system fault exception context state capture. More...
struct	stk::FaultContext::Mpu
	Hardware Memory Protection Unit (MPU) status register snapshot. More...
struct	stk::FaultContext::Mpu::Region
	Register snapshot for an individual hardware MPU region slot. More...

Namespaces
namespace	stk
	Namespace of STK package.
namespace	stk::hw
	Hardware Abstraction Layer (HAL) for architecture-specific operations.

Macros
#define	STK_ARCH_ARMV6_M   (0)
	ARMv6-M platform (Cortex-M0, Cortex-M0+, Cortex-M1).
#define	STK_ARCH_ARMV7_M   (0)
	ARMv7-M platform (Cortex-M3, Cortex-M4, Cortex-M7).
#define	STK_ARCH_ARMV8_M   (0)
	ARMv8-M platform (Cortex-M23, Cortex-M33, Cortex-M55, Cortex-M85).
#define	STK_TZ_SECURE   (0)
	ARM TrustZone: Defines Secure (1) build.
#define	STK_TZ_NON_SECURE   (0)
	ARM TrustZone: Defines Non-Secure (1) build.
#define	__stk_tz_nsc_entry
	ARM TrustZone: attribute for Non-Secure callable gateway functions.
#define	__stk_tz_ns_call
	ARM TrustZone: attribute for calling Non-Secure functions from Secure state.
#define	STK_TZ_NSC_GATEWAY   extern "C" __stk_tz_nsc_entry
#define	STK_CORTEX_M_MPU_REGIONS_MAX   (8U)
	Number of MPU regions supported by MPU peripheral.
#define	STK_MPU_SHARED_DATA_SECTION
#define	STK_MPU_SHARED_CODE_SECTION
#define	STK_MPU_SHARED_BSS_SECTION

Typedefs
typedef PlatformArmCortexM	stk::PlatformDefault
	Default platform implementation.

Functions
static void	__stk_dmb ()
	Hardware memory barrier: ensures visibility across cores and bus masters.

Detailed Description

Platform port for ARM Cortex-M.

Definition in file stk_arch_arm-cortex-m.h.

Macro Definition Documentation

__stk_tz_ns_call

#define __stk_tz_ns_call

ARM TrustZone: attribute for calling Non-Secure functions from Secure state.

Definition at line 107 of file stk_arch_arm-cortex-m.h.

__stk_tz_nsc_entry

#define __stk_tz_nsc_entry

ARM TrustZone: attribute for Non-Secure callable gateway functions.

Note

Places the function in the .nsc_entry section mapped to the NSC region.

Definition at line 98 of file stk_arch_arm-cortex-m.h.

STK_ARCH_ARMV6_M

#define STK_ARCH_ARMV6_M   (0)

ARMv6-M platform (Cortex-M0, Cortex-M0+, Cortex-M1).

Definition at line 25 of file stk_arch_arm-cortex-m.h.

STK_ARCH_ARMV7_M

#define STK_ARCH_ARMV7_M   (0)

ARMv7-M platform (Cortex-M3, Cortex-M4, Cortex-M7).

Definition at line 40 of file stk_arch_arm-cortex-m.h.

STK_ARCH_ARMV8_M

#define STK_ARCH_ARMV8_M   (0)

ARMv8-M platform (Cortex-M23, Cortex-M33, Cortex-M55, Cortex-M85).

Definition at line 55 of file stk_arch_arm-cortex-m.h.

STK_CORTEX_M_MPU_REGIONS_MAX

#define STK_CORTEX_M_MPU_REGIONS_MAX   (8U)

Number of MPU regions supported by MPU peripheral.

Definition at line 131 of file stk_arch_arm-cortex-m.h.

STK_MPU_SHARED_BSS_SECTION

#define STK_MPU_SHARED_BSS_SECTION

Definition at line 471 of file stk_arch_arm-cortex-m.h.

STK_MPU_SHARED_CODE_SECTION

#define STK_MPU_SHARED_CODE_SECTION

Definition at line 470 of file stk_arch_arm-cortex-m.h.

STK_MPU_SHARED_DATA_SECTION

#define STK_MPU_SHARED_DATA_SECTION

Definition at line 469 of file stk_arch_arm-cortex-m.h.

STK_TZ_NON_SECURE

#define STK_TZ_NON_SECURE   (0)

ARM TrustZone: Defines Non-Secure (1) build.

Definition at line 88 of file stk_arch_arm-cortex-m.h.

STK_TZ_NSC_GATEWAY

#define STK_TZ_NSC_GATEWAY   extern "C" __stk_tz_nsc_entry

Definition at line 113 of file stk_arch_arm-cortex-m.h.

STK_TZ_SECURE

#define STK_TZ_SECURE   (0)

ARM TrustZone: Defines Secure (1) build.

Definition at line 79 of file stk_arch_arm-cortex-m.h.

Function Documentation

__stk_dmb()

void __stk_dmb ( )

inlinestatic

Hardware memory barrier: ensures visibility across cores and bus masters.

Definition at line 136 of file stk_arch_arm-cortex-m.h.

{ __asm volatile("dmb sy" ::: "memory"); }

References __stk_forceinline.